1. Field of the Invention
The present invention generally relates to bipolar transistors. More particularly, the present invention relates to performance characteristics of a bipolar transistor at the interface between an emitter region and an emitter electrode of the bipolar transistor.
2. Description of the Related Art
FIG. 1 is a cross-sectional view of a conventional vertical bipolar transistor. In this example, an NPN transistor is shown, and accordingly, an N+ buried collector region 2 is located at a depth within a N− collector region 3 formed over a P− substrate 1. Typically, the N− collector region 3 is formed by epitaxial growth over the P− substrate 1. Also, as shown, LOCOS or STI insulating layers 4 are formed to isolate surface regions of the N− collector region 3.
A P+ base layer 5 is formed by epitaxial growth of single-crystal Si or SiGe over the N− collector region 3, and an N+ emitter region 6 is formed by doping impurities to a given depth within the P+ base layer 5. A P+ poly-silicon base electrode 7 and an N+ poly-silicon emitter electrode 8 respectively contact surfaces of the base region 5 and emitter region 6. The emitter region 6 is usually formed by diffusion of impurities from the poly-silicon emitter electrode 8 into the base region 5. The poly-silicon emitter electrode 8 is electrically insulated from the poly-silicon base electrode 7 by sidewall spacers 9 and insulating layer 10. Further, each of the poly-silicon base and emitter electrodes 7, 8 is covered with a silicide layer 11 for low-resistance contact to a metal interconnect (not shown).
An overdoped N+ region 12 is located below the emitter region 6 and extends between the base region 5 and the N+ buried collector region 2. Likewise, an N+ collector sink 13 extends from the N+ buried collector region 2 to the surface of the device for connection to a metal collector contact (not shown) via the silicide layer 11.
As is well know in the art, conductivity of the bipolar transistor is achieved by the injection of minority carriers from the emitter region 6 into the base region 5, thereby electrically connecting the emitter region 6 to the underlying N+ collector region 12. In this state, an electrical path is established from the emitter electrode 8 to the collector sink 13 via the overdoped collector region 12 and the buried collector region 2.
Various techniques have been applied in the art in an effort to enhance performance characteristics of the bipolar transistor. For example, a so-called heterojunction bipolar transistor is known in which the emitter region is formed with a higher band gap than the underlying base region, thus facilitating the injection of minority carriers into the base region. One exemplary heterojunction device is formed by stacking epitaxially grown layers SiGe and Si over the collector region, and then doping a region of the upper Si layer to define the emitter. The bandgap of the Si emitter is wider than that of SiGe base, thus enhancing injection efficiency. It is also known that injection efficiency can be further enhanced by providing a graded distribution of Ge in the SiGe layer to achieve a non-uniform band-gap.
Notwithstanding these and other improvements relating to the emitter characteristics within the base, there still exist a demand for bipolar transistors having higher performance efficiencies.
Returning to FIG. 1, the conventional configuration is characterized by the deposition of doped poly-silicon between the sidewall spacers 8 and over the insulating layer 26. This doped poly-silicon directly contacts the emitter region 6 and forms the emitter electrode 8 of the transistor.
As mentioned above, the emitter region 6 is usually formed by diffusion of impurities from the deposited emitter electrode into the base region 5. As also mentioned above, the base region 5 is formed by epitaxial growth of single-crystal Si and/or SiGe over the collector region 3. As such, the poly-crystalline structure of the gate electrode 8 directly contacts the single-crystalline structure of the emitter region 6. This abrupt change in crystalline structure creates a resistive component at the interface between the emitter region 6 and the emitter electrode 8. This resistive component appears in the conductive path of the transistor, thus degrading performance.
Further, due to process limitations, the deposition of poly-silicon directly onto the emitter region results in substantial defects at the interface between the two. These defects further increase the resistive component at the interface.